There are many researches related to the design of power delivery network (Power Delivery Network, or Power Distribution Network, or Power Network, hereinafter all referred to as “PDN”). Generally speaking, there are many nodes in the PDN. The quality of PDN are mainly influenced by the resistance of the transmission line, i.e. when current flowing through a section of the transmission line, because of the presence the resistance, the voltage drop would be generated. The voltage drop is also known as IR drop (“I” represents current and “R” represents resistance). The voltage drop would lower the stability of the circuit system, and even cause the error of the circuit. For example, in an integrated circuit (IC), large voltage drop happened in the PDN would cause malfunction of the IC. And, the quality of the PDN would influence the power integrity (PI) of the IC.
Normally, the design of the PDN would be in uniform type. For example, horizontal/vertical power stripes of the PDN have the same spacing and width. Owing to the large voltage drop, the power supply may be not enough since different areas have different power supply requirements. Or, the power supply would be overdesigned which wasting signal winding resources. To avoid the above issues are engaged by industry.
FIG. 1 illustrates a flow diagram of a current integrated circuit design (hereinafter referred to as “IC design”). The current IC design includes circuit design step 102, floorplan and PDN design step 104, circuit unit placement and clock tree generation step 106, routing step 108, and power analysis step 110. After power analysis step 110, if it is necessary to provide power distribution network adjustment, the designer should go back to the floorplan and PDN design step 104 from power analysis step 110 to redesign the PDN, for instance, to increase the dense of the PDN or to widen the line width of the PDN or to increase the numbers of the power sources. When redesigning, step 104 to step 110 should be repeated with lengthy turn-around time. The total IC design time will be lengthened. If the designer repeats redesigning for several times, it may cause a significant delay in the IC design process.